Chip Design: Building a Systolic Array TPU in Vivado

This demo walks through the full chip design cycle for a 16×16 INT8 systolic-array TPU,
completed in a single Vivado session with CopperPilot. The flow starts with planning,
moves through RTL generation and simulation, and ends with synthesis report analysis,
timing-oriented fixes, and architecture-level performance framing.

Overview

Instead of jumping straight into Verilog, CopperPilot starts with a spec-first approach
inside Vivado. It studies similar designs, defines interfaces, plans modules, proposes a
verification strategy, and documents edge cases such as stalls, overflow, signed arithmetic,
and back-to-back input behavior.

Workflow

1. Spec-first planning: Generate a written engineering spec before touching
   RTL, including architecture choices like an output-stationary flow.
2. Implementation and first pass test: Create core modules (processing
   element, 16×16 array, buffers, top module, and testbench), then run simulation.
3. Fast debug loop: Parse tool errors, fix issues, and re-run compile/sim
   quickly without leaving the design environment.
4. Waveform and activity inspection: Use Vivado xsim to observe both math
   correctness and compute wavefront behavior across the array.
5. Synthesis and report-driven refinement: Choose out-of-context synthesis,
   inspect full reports, then apply targeted timing-aware fixes.

Key Technical Highlights

• 16×16 INT8 systolic array with 256 processing elements and DSP58 mapping visibility.
• Activity observability with a 256-bit activity marker and active-MAC count per cycle.
• Edge-case validation for identity, all-zero, stress inputs, mid-run stalls, and immediate back-to-back data.
• Synthesis quality improvements by replacing asynchronous reset patterns and adding multiplier pipelining.
• Post-fix flow shows cleaner DSP inference and healthier timing paths for implementation readiness.

Outcome

By combining specification, implementation, verification, and synthesis analysis in one loop,
CopperPilot helps teams move from concept to hardware-ready design faster while keeping the
engineer in control of architectural decisions. Performance scales with clock frequency, and
this 8-bit class design can be positioned in the TinyML range while remaining parameterizable
for larger targets.